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drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 drv84x2 dual full-bridge pwm motor driver the drv841x2 requires two power supplies, one at 1 features 12 v for gvdd and vdd, and another up to 50 v for 1 ? high-efficiency power stage (up to 97%) with pvdd. the drv841x2 can operate at up to 500-khz low r ds(on) mosfets (110 m ? at t j = 25 c) switching frequency while still maintaining precise ? operating supply voltage up to 52 v control and high efficiency. the devices also have an innovative protection system safeguarding the device ? drv8412 (power pad down): up to 2 3-a against a wide range of fault conditions that could continuous output current (2 6-a peak) in dual damage the system. these safeguards are short- full-bridge mode or 6-a continuous current in circuit protection, overcurrent protection, undervoltage parallel mode (12-a peak) protection, and two-stage thermal protection. the ? drv8432 (power pad up): up to 2 7-a drv841x2 has a current-limiting circuit that prevents continuous output current (2 12-a peak) in device shutdown during load transients such as motor dual full-bridge mode or 14-a continuous start-up. a programmable overcurrent detector allows adjustable current limit and protection level to meet current in parallel mode (24-a peak) different motor requirements. ? pwm operating frequency up to 500 khz the drv841x2 has unique independent supply and ? integrated self-protection circuits including ground pins for each half-bridge. these pins make it undervoltage, overtemperature, overload, and possible to provide current measurement through short circuit external shunt resistor and support multiple motors ? programmable cycle-by-cycle current limit with different power supply voltage requirements. protection ? independent supply and ground pins for each device information (1) half bridge part number package body size (nom) ? intelligent gate drive and cross conduction drv8412 htssop (44) 14.00 mm x 6.10 mm prevention drv8432 hssop (36) 15.90 mm x 11.00 mm ? no external snubber or schottky diode is (1) for all available packages, see the orderable addendum at required the end of the data sheet. simplified application diagram 2 applications ? brushed dc and stepper motors ? three-phase permanent magnet synchronous motors ? robotic and haptic control system ? actuators and pumps ? precision instruments ? tec drivers ? led lighting drivers 3 description the drv841x2 are high-performance, integrated dual full-bridge motor driver with an advanced protection system. because of the low r ds(on) of the h-bridge mosfets and intelligent gate drive design, the efficiency of these motor drivers can be up to 97%. this high efficiency enables the use of smaller power supplies and heatsinks, and the devices are good candidates for energy-efficient applications. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. gvdd gvdd pvdd pvdd m m controller reset_ab pwm_b oc_adj gnd gnd_agnd_b out_b pvdd_b agnd vreg m3m2 bst_b bst_c pvdd_c out_c reset_cd pwm_d vdd gvdd_c out_d pvdd_d bst_d gvdd_d pwm_c gnd_d m1 gnd_c gvdd_b otw fault pwm_a gvdd_a bst_a pvdd_a out_a productfolder sample &buy technical documents tools & software support &community
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com table of contents 1 features .................................................................. 1 8 application and implementation ........................ 17 8.1 application information ............................................ 17 2 applications ........................................................... 1 8.2 typical applications ................................................ 17 3 description ............................................................. 1 9 power supply recommendations ...................... 24 4 revision history ..................................................... 2 9.1 bulk capacitance .................................................... 24 5 pin configuration and functions ......................... 4 9.2 power supplies ....................................................... 24 6 specifications ......................................................... 6 9.3 system power-up and power-down sequence ..... 25 6.1 absolute maximum ratings ...................................... 6 9.4 system design recommendations ......................... 25 6.2 esd ratings ............................................................ 6 10 layout ................................................................... 27 6.3 recommended operating conditions ....................... 6 10.1 layout guidelines ................................................. 27 6.4 thermal information .................................................. 7 10.2 layout example .................................................... 27 6.5 package heat dissipation ratings ............................ 7 10.3 thermal considerations ........................................ 30 6.6 package power deratings (drv8412) ..................... 7 11 device and documentation support ................. 32 6.7 electrical characteristics ........................................... 8 11.1 related links ........................................................ 32 6.8 typical characteristics .............................................. 9 11.2 trademarks ........................................................... 32 7 detailed description ............................................ 10 11.3 electrostatic discharge caution ............................ 32 7.1 overview ................................................................. 10 11.4 glossary ................................................................ 32 7.2 functional block diagram ....................................... 11 12 mechanical, packaging, and orderable 7.3 feature description ................................................. 12 information ........................................................... 32 7.4 device functional modes ........................................ 15 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision f (january 2014) to revision g page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ................................................................................................. 1 changes from revision e (october 2013) to revision f page ? changed gnd_a, gnd_b, gnd_c, and gnd_d pins description to remove text " requires close decoupling capacitor to ground " ................................................................................................................................................................ 4 ? changed the t on_min description to include " for charging the bootstrap capacitor " ................................................................ 6 ? added text to the overcurrent (oc) protection section - " it is important to note... " ............................................................ 13 changes from revision d (july 2011) to revision e page ? added last sentence in description of thermal pad in pin functions table. .......................................................................... 5 ? added thermal information table ................................................................................................................................ 7 ? added a new paragraph in different operational modes section: in operation modes.....dc logic level. ........... 15 changes from revision c (may 2010) to revision d page ? changed from 80 m to 110 m in first feature ................................................................................................................... 1 ? changed from 50 v to 52 v in second feature ...................................................................................................................... 1 ? deleted (70 v absolute maximum) from second feature ...................................................................................................... 1 ? added led lighting drivers to applications ........................................................................................................................... 1 ? added includes metallization bond wire and pin resistance to r ds(on) test conditions ........................................................... 8 ? changed r ds(on) typ from 80 m to 110 m .......................................................................................................................... 8 2 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 ? added text to 5th paragraph of overcurrent (oc) protection section .................................................................................. 13 ? deleted output inductor selection section and moved information into overcurrent (oc) protection section .................... 13 ? changed figure 8 ................................................................................................................................................................. 17 ? changed figure 16 .............................................................................................................................................................. 21 ? deleted application diagram example for three phase pmsm pvdd sense operation and application diagram example for three phase pmsm gnd sense operation figures ........................................................................................ 22 ? added figure 18 .................................................................................................................................................................. 23 ? changed figure 20 .............................................................................................................................................................. 28 changes from revision b (jan 2010) to revision c page ? deleted all drv8422 related descriptions from this data sheet ............................................................................................. 1 ? changed drv8432 pinout ...................................................................................................................................................... 4 ? added thermal pad and heat slug rows to end of pin functions table. also added t=thermal in note ............................... 5 ? added second paragraph to bootstrap capacitor....section ................................................................................................. 12 ? deleted or gvdd undervoltage from device reset section second paragraph ............................................................. 14 changes from revision a (december 2009) to revision b page ? added t a = 125 c power rating of 1.0 w to package power deratings table ........................................................................ 7 copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 5 pin configuration and functions pin functions pin i/o type (1) description name drv8412 drv8432 agnd 12 9 p analog ground bst_a 24 35 p high side bootstrap supply (bst), external capacitor to out_a required bst_b 33 28 p high side bootstrap supply (bst), external capacitor to out_b required bst_c 34 27 p high side bootstrap supply (bst), external capacitor to out_c required bst_d 43 20 p high side bootstrap supply (bst), external capacitor to out_d required gnd 13 8 p ground gnd_a 29 32 p power ground for half-bridge a gnd_b 30 31 p power ground for half-bridge b gnd_c 37 24 p power ground for half-bridge c gnd_d 38 23 p power ground for half-bridge d gvdd_a 23 36 p gate-drive voltage supply gvdd_b 22 1 p gate-drive voltage supply gvdd_c 1 18 p gate-drive voltage supply gvdd_d 44 19 p gate-drive voltage supply m1 8 13 i mode selection pin m2 9 12 i mode selection pin m3 10 11 i reserved mode selection pin, agnd connection is recommended nc 3, 4, 19, 20, 25, 42 ? ? no connection pin. ground connection is recommended oc_adj 14 7 o analog overcurrent programming pin, requires resistor to agnd otw 21 2 o overtemperature warning signal, open-drain, active-low. an internal pullup resistor to vreg (3.3 v) is provided on output. level compliance for 5-v logic can be obtained by adding external pullup resistor to 5 v out_a 28 33 o output, half-bridge a out_b 31 30 o output, half-bridge b out_c 36 25 o output, half-bridge c (1) i = input, o = output, p = power, t = thermal 4 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 gvdd_c vdd ncnc pwm_d reset_cd pwm_c oc_adj gnd agnd vreg m3 m2 m1 pwm_b reset_ab pwm_a nc fault nc otw gvdd_b drv8412 ddw package (top view) gvdd_dbst_d nc pvdd_d pvdd_d out_d gnd_d gnd_c out_c pvdd_cbst_c bst_b pvdd_b out_b gnd_b gnd_a out_a pvdd_a pvdd_a nc bst_a gvdd_a 44 43 42 41 40 3938 37 36 35 34 33 32 31 30 2928 27 26 25 24 23 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 2928 27 26 25 24 23 22 21 20 19 gvdd_b fault reset_ab reset_cd pwm_b pwm_d pwm_c otw gnd pwm_a agnd oc_adj m3 vdd gvdd_c vreg m2 m1 gvdd_abst_a pvdd_a out_a gnd_a gnd_b out_b pvdd_b bst_b pvdd_c bst_cout_c gnd_c gnd_d out_d pvdd_d bst_d gvdd_d drv8432 dkd package (top view)
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 pin functions (continued) pin i/o type (1) description name drv8412 drv8432 out_d 39 22 o output, half-bridge d pvdd_a 26, 27 34 p power supply input for half-bridge a requires close decoupling capacitor to ground. pvdd_b 32 29 p power supply input for half-bridge b requires close decoupling capacitor to gound. pvdd_c 35 26 p power supply input for half-bridge c requires close decoupling capacitor to ground. pvdd_d 40, 41 21 p power supply input for half-bridge d requires close decoupling capacitor to ground. pwm_a 17 4 i input signal for half-bridge a pwm_b 15 6 i input signal for half-bridge b pwm_c 7 14 i input signal for half-bridge c pwm_d 5 16 i input signal for half-bridge d reset_ab 16 5 i reset signal for half-bridge a and half-bridge b, active-low reset_cd 6 15 i reset signal for half-bridge c and half-bridge d, active-low fault 18 3 o fault signal, open-drain, active-low. an internal pullup resistor to vreg (3.3 v) is provided on output. level compliance for 5-v logic can be obtained by adding external pullup resistor to 5 v vdd 2 17 p power supply for digital voltage regulator requires capacitor to ground for decoupling. vreg 11 10 p digital regulator supply filter pin requires 0.1- f capacitor to agnd. thermal pad ? n/a t solder the exposed thermal pad to the landing pad on the pcb. connect landing pad to bottom side of pcb through via for better thermal dissipation. this pad should be connected to gnd. heat slug n/a ? t mount heat sink with thermal interface on top of the heat slug for best thermal performance. mode selection pins mode pins output description configuration m3 m2 m1 dual full bridges (two pwm inputs each full bridge) or four half bridges with 0 0 0 2 fb or 4 hb cycle-by-cycle current limit dual full bridges (two pwm inputs each full bridge) or four half bridges with 0 0 1 2 fb or 4 hb oc latching shutdown (no cycle-by-cycle current limit) 0 1 0 1 pfb parallel full bridge with cycle-by-cycle current limit dual full bridges (one pwm input each full bridge with complementary pwm 0 1 1 2 fb on second half bridge) with cycle-by-cycle current limit 1 x x reserved copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit vdd to gnd ? 0.3 13.2 v gvdd_x to gnd ? 0.3 13.2 v pvdd_x to gnd_x (2) ? 0.3 70 v out_x to gnd_x (2) ? 0.3 70 v bst_x to gnd_x (2) ? 0.3 80 v transient peak output current (per pin), pulse width limited by 16 a internal overcurrent protection circuit transient peak output current for latch shut down (per pin) 20 a vreg to agnd ? 0.3 4.2 v gnd_x to gnd ? 0.3 0.3 v gnd to agnd ? 0.3 0.3 v pwm_x to gnd ? 0.3 v reg + 0.5 v oc_adj, m1, m2, m3 to agnd ? 0.3 4.2 v reset_x, fault, otw to gnd ? 0.3 7 v continuous sink current ( fault, otw) 9 ma operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 55 150 (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) these are the maximum allowed voltages for transient spikes. absolute maximum dc voltages are lower. 6.2 esd ratings value unit charged device model (cdm), per jedec specification jesd22-c101, v (esd) electrostatic discharge 1500 v all pins (1) (1) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit pvdd_x half bridge x (a, b, c, or d) dc supply voltage 0 50 52.5 gvdd_x supply for logic regulators and gate-drive circuitry 10.8 12 13.2 v vdd digital regulator supply voltage 10.8 12 13.2 i o_pulse pulsed peak current per output pin (could be limited by thermal) 15 a i o continuous current per output pin (drv8432) 9 ma f sw pwm switching frequency 500 khz r ocp_cbc oc programming resistor range in cycle-by-cycle current limit modes 24 200 k ? r ocp_ocl oc programming resistor range in oc latching shutdown modes 22 200 c bst bootstrap capacitor range 33 220 nf t on_min minimum pwm pulse duration, low side, for charging the bootstrap capacitor 50 ns t a operating ambient temperature ? 40 85 c 6 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 6.4 thermal information drv8412 drv8432 ddw dkd thermal metric (1) unit package package 44 pins 36 pins 13.3 r ja junction-to-ambient thermal resistance 24.5 (with heat sink) r jc(top) junction-to-case (top) thermal resistance 7.8 0.4 r jb junction-to-board thermal resistance 5.5 13.3 c/w jt junction-to-top characterization parameter 0.1 0.4 jb junction-to-board characterization parameter 5.4 13.3 r jc(bot) junction-to-case (bottom) thermal resistance 0.2 n/a (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.5 package heat dissipation ratings parameter drv8412 drv8432 r jc , junction-to-case (power pad / heat slug) thermal 1.1 c/w 0.9 c/w resistance this device is not intended to be used without a r ja , junction-to-ambient thermal resistance 25 c/w heatsink. therefore, r ja is not specified. see the thermal information section. exposed power pad / heat slug area 34 mm 2 80 mm 2 6.6 package power deratings (drv8412) (1) derating t a = 25 c factor t a = 70 c power t a = 85 c power t a = 125 c power package power above t a = rating rating rating rating 25 c 44-pin tssop (ddw) 5.0 w 40.0 mw/ c 3.2 w 2.6 w 1.0 w (1) based on evm board layout copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 6.7 electrical characteristics t a = 25 c, pvdd = 50 v, gvdd = vdd = 12 v, f sw = 400 khz, unless otherwise noted. all performance is in accordance with recommended operating conditions unless otherwise specified. parameter test conditions min typ max unit internal voltage regulator and current consumption v reg voltage regulator, only used as a reference node vdd = 12 v 2.95 3.3 3.65 v idle, reset mode 9 12 ma i vdd vdd supply current operating, 50% duty cycle 10.5 reset mode 1.7 2.5 ma i gvdd_x gate supply current per half-bridge operating, 50% duty cycle 8 i pvdd_x half-bridge x (a, b, c, or d) idle current reset mode 0.7 1 ma output stage t j = 25 c, gvdd = 12 v, includes metallization mosfet drain-to-source resistance, low side (ls) 110 bond wire and pin resistance r ds(on) m ? t j = 25 c, gvdd = 12 v, includes metallization mosfet drain-to-source resistance, high side (hs) 110 bond wire and pin resistance v f diode forward voltage drop t j = 25 c - 125 c, i o = 5 a 1 v t r output rise time resistive load, i o = 5 a 14 t f output fall time resistive load, i o = 5 a 14 t pd_on propagation delay when fet is on resistive load, i o = 5 a 38 ns t pd_off propagation delay when fet is off resistive load, i o = 5 a 38 t dt dead time between hs and ls fets resistive load, i o = 5 a 5.5 i/o protection gate supply voltage gvdd_x undervoltage v uvp,g 8.5 protection threshold v v uvp,hyst (1) hysteresis for gate supply undervoltage event 0.8 otw (1) overtemperature warning 115 125 135 otw hyst (1) hysteresis temperature to reset otw event 25 otsd (1) overtemperature shut down 150 c ote- ote-otw overtemperature detect temperature 25 otw differential (1) difference hysteresis temperature for fault to be released otsd hyst (1) 25 following an otsd event i oc overcurrent limit protection resistor ? programmable, nominal, r ocp = 27 k ? 9.7 a time from application of short condition to hi-z of i oct overcurrent response time 250 ns affected fet(s) internal pulldown resistor at the output of each half- connected when reset_ab or reset_cd is r pd 1 k ? bridge active to provide bootstrap capacitor charge static digital specifications v ih high-level input voltage pwm_a, pwm_b, pwm_c, pwm_d, m1, m2, m3 2 3.6 v ih high-level input voltage reset_ab, reset_cd 2 5.5 v pwm_a, pwm_b, pwm_c, pwm_d, m1, m2, m3, v il low-level input voltage 0.8 reset_ab, reset_cd l lkg input leakage current ? 100 100 a otw / fault internal pullup resistance, otw to vreg, fault to r int_pu 20 26 35 k ? vreg internal pullup resistor only 2.95 3.3 3.65 v oh high-level output voltage external pullup of 4.7 k ? to 5 v 4.5 5 v v ol low-level output voltage i o = 4 ma 0.2 0.4 (1) specified by design 8 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 6.8 typical characteristics full bridge load = 5 a pvdd = 50 v t c = 75 c t j = 25 c figure 1. efficiency vs switching frequency (drv8432) figure 2. normalized rds(on) vs gate drive t j = 25 c gvdd = 12 v figure 4. drain to source diode forward on characteristics figure 3. normalized rds(on) vs junction temperature f s = 500 khz t c = 25 c figure 5. output duty cycle vs input duty cycle copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: drv8412 drv8432 0 100 10 20 30 40 50 60 70 80 90 output duty cycle (%) input duty cycle (%) 90 60 100 0 70 40 20 10 30 50 80 1.6 0.4 0.6 0.8 1.0 t C junction temperature C c j o normalized r / (r at 25 c) ds(on) ds(on) o 80 40 120 C40 60 20 C20 0 100 1.2 1.4 140 C1 5 0 1 2 3 voltage (v) current (a) 1.2 0.8 0 1 0.6 0.2 0.4 4 6 0 100 40 50 60 70 80 90 efficiency (%) switching frequency (khz) 0 100 150 200 250 300 350 400 450 500 50 10 20 30 1.10 0.96 1.00 0.98 1.02 1.04 gate drive (v) normalized r / (r at 12 v) ds(on) ds(on) 11.0 10.0 8.0 10.5 9.5 8.5 9.0 11.5 1.06 1.08 12
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 7 detailed description 7.1 overview the drv841x2 is a high performance, integrated dual full bridge motor driver with an advanced protection system. because of the low r ds(on) of the h-bridge mosfets and intelligent gate drive design, the efficiency of these motor drivers can be up to 97%, which enables the use of smaller power supplies and heatsinks, and are good candidates for energy efficient applications. 10 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 7.2 functional block diagram copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: drv8412 drv8432 temp. sense m1 m2 reset_ab fault otw agndoc_adj vreg vreg vdd m3 power on reset under- voltage protection gnd pwm_d out_dgnd_d pvdd_d bst_d timing gate drive pwm rcv. overload protection i sense gvdd_d reset_cd 4 protection and i/o logic pwm_c out_cgnd_c pvdd_c bst_c timing gate drive ctrl. pwm rcv. gvdd_c pwm_b out_bgnd_b pvdd_b bst_b timing gate drive ctrl. pwm rcv. gvdd_b pwm_a out_agnd_a pvdd_a bst_a timing gate drive ctrl. pwm rcv. gvdd_a ctrl. fb/pfb?configuration pulldown resistor fb/pfb?configuration pulldown resistor fb/pfb?configuration pulldown resistor fb/pfb?configuration pulldown resistor internal pullup resistors to vreg 4
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 7.3 feature description 7.3.1 error reporting the fault and otw pins are both active-low, open-drain outputs. their function is for protection-mode signaling to a pwm controller or other system-control device. any fault resulting in device shutdown, such as overtemperatue shutdown, overcurrent shutdown, or undervoltage protection, is signaled by the fault pin going low. likewise, otw goes low when the device junction temperature exceeds 125 c (see table 1 ). table 1. protection mode signal descriptions fault otw description 0 0 overtemperature warning and (overtemperature shut-down or overcurrent shut-down or undervoltage protection) occurred 0 1 overcurrent shut-down or gvdd undervoltage protection occurred 1 0 overtemperature warning 1 1 device under normal operation ti recommends monitoring the otw signal using the system microcontroller and responding to an otw signal by reducing the load current to prevent further heating of the device resulting in device overtemperature shutdown (otsd). to reduce external component count, an internal pullup resistor to vreg (3.3 v) is provided on both fault and otw outputs. level compliance for 5-v logic can be obtained by adding external pullup resistors to 5 v (see the electrical characteristics section of this data sheet for further specifications). 7.3.2 device protection system the drv841x2 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overcurrent, overtemperature, and undervoltage. the drv841x2 responds to a fault by immediately setting the half bridge outputs in a high-impedance (hi-z) state and asserting the fault pin low. in situations other than overcurrent or overtemperature, the device automatically recovers when the fault condition has been removed or the gate supply voltage has increased. for highest possible reliability, reset the device externally no sooner than 1 second after the shutdown when recovering from an overcurrent shut down (ocsd) or otsd fault. 7.3.2.1 bootstrap capacitor undervoltage protection when the device runs at a low switching frequency (for example, less than 10 khz with a 100-nf bootstrap capacitor), the bootstrap capacitor voltage might not be able to maintain a proper voltage level for the high-side gate driver. a bootstrap capacitor undervoltage protection circuit (bst_uvp) will prevent potential failure of the high-side mosfet. when the voltage on the bootstrap capacitors is less than the required value for safe operation, the drv841x2 will initiate bootstrap capacitor recharge sequences (turn off high side fet for a short period) until the bootstrap capacitors are properly charged for safe operation. this function may also be activated when pwm duty cycle is too high (for example, less than 20 ns off time at 10 khz). note that bootstrap capacitor might not be able to be charged if no load or extremely light load is presented at output during bst_uvp operation, so it is recommended to turn on the low side fet for at least 50 ns for each pwm cycle to avoid bst_uvp operation if possible. for applications with lower than 10-khz switching frequency and not to trigger bst_uvp protection, a larger bootstrap capacitor can be used (for example, 1- f capacitor for 800-hz operation). when using a bootstrap cap larger than 220 nf, it is recommended to add 5- resistors between 12-v gvdd power supply and gvdd_x pins to limit the inrush current on the internal bootstrap circuitry. 7.3.2.2 overcurrent (oc) protection the drv841x2 has independent, fast-reacting current detectors with programmable trip threshold (oc threshold) on all high-side and low-side power-stage fets. there are two settings for oc protection through mode selection pins: cycle-by-cycle (cbc) current limiting mode and oc latching (ocl) shut down mode. 12 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 feature description (continued) in cbc current limiting mode, the detector outputs are monitored by two protection systems. the first protection system controls the power stage in order to prevent the output current from further increasing, that is, it performs a cbc current-limiting function rather than prematurely shutting down the device. this feature could effectively limit the inrush current during motor start-up or transient without damaging the device. during short to power and short to ground conditions, the current limit circuitry might not be able to control the current to a proper level, a second protection system triggers a latching shutdown, resulting in the related half bridge being set in the high- impedance (hi-z) state. current limiting and overcurrent protection are independent for half-bridges a, b, c, and, d, respectively. figure 6 illustrates cycle-by-cycle operation with high side oc event and figure 7 shows cycle-by-cycle operation with low side oc. dashed lines are the operation waveforms when no cbc event is triggered and solid lines show the waveforms when cbc event is triggered. in cbc current limiting mode, when low side fet oc is detected, the device will turn off the affected low side fet and keep the high side fet at the same half bridge off until the next pwm cycle; when high side fet oc is detected, the device will turn off the affected high side fet and turn on the low side fet at the half bridge until next pwm cycle. it is important to note that if the input to a half bridge is held to a constant value when an over current event occurs in cbc, then the associated half bridge will be in a hi-z state upon the over current event ending. cycling in_x will allow out_x to resume normal operation. in oc latching shut down mode, the cbc current limit and error recovery circuits are disabled and an overcurrent condition will cause the device to shutdown immediately. after shutdown, reset_ab and/or reset_cd must be asserted to restore normal operation after the overcurrent condition is removed. for added flexibility, the oc threshold is programmable using a single external resistor connected between the oc_adj pin and gnd pin. see table 2 for information on the correlation between programming-resistor value and the oc threshold. the values in table 2 show typical oc thresholds for a given resistor. assuming a fixed resistance on the oc_adj pin across multiple devices, a 20% device-to-device variation in oc threshold measurements is possible. therefore, this feature is designed for system protection and not for precise current control. it should be noted that a properly functioning overcurrent detector assumes the presence of a proper inductor or power ferrite bead at the power-stage output. short-circuit protection is not guaranteed with direct short at the output pins of the power stage. for normal operation, inductance in motor (assume larger than 10 h) is sufficient to provide low di/dt output (for example, for emi) and proper protection during overload condition (cbc current limiting feature). so no additional output inductors are needed during normal operation. however during a short condition, the motor (or other load) is shorted, so the load inductance is not present in the system anymore; the current in the device can reach such a high level that may exceed the abs max current rating due to extremely low impendence in the short circuit path and high di/dt before oc detection circuit kicks in. so a ferrite bead or inductor is recommended to use the short-circuit protection feature in drv841x2. with an external inductance or ferrite bead, the current will rise at a much slower rate and reach a lower current level before oc protection starts. the device will then either operate cbc current limit or oc shut down automatically (when current is well above the current limit threshold) to protect the system. for a system that has limited space, a power ferrite bead can be used instead of an inductor. the current rating of ferrite bead has to be higher than the rms current of the system at normal operation. a ferrite bead designed for very high frequency is not recommended. a minimum impedance of 10 or higher is recommended at 10 mhz or lower frequency to effectively limit the current rising rate during short circuit condition. the tdk mpz2012s300a (with size of 0805 inch type) have been tested in our system to meet a short circuit condition in the drv8412. but other ferrite beads that have similar frequency characteristics can be used as well. for higher power applications, such as in the drv8432, there might be limited options to select suitable ferrite bead with high current rating. if an adequate ferrite bead cannot be found, an inductor can be used. the inductance can be calculated as: where ? toc_delay = 250 ns copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: drv8412 drv8432 _ _ min pvdd toc delay loc ipeak iave = -
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com feature description (continued) ? ipeak = 15 a (below abs max rating) (1) because an inductor usually saturates after reaching its current rating, it is recommended to use an inductor with a doubled value or an inductor with a current rating well above the operating condition. table 2. programming-resistor values and oc threshold oc-adjust resistor maximum current before oc values (k ? ) occurs (a) 22 (1) 11.6 24 10.7 27 9.7 30 8.8 36 7.4 39 6.9 43 6.3 47 5.8 56 4.9 68 4.1 82 3.4 100 2.8 120 2.4 150 1.9 200 1.4 (1) recommended to use in oc latching mode only 7.3.2.3 overtemperature protection the drv841x2 has a two-level temperature-protection system that asserts an active-low warning signal ( otw) when the device junction temperature exceeds 125 c (nominal) and, if the device junction temperature exceeds 150 c (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high- impedance (hi-z) state and fault being asserted low. otsd is latched in this case and reset_ab and reset_cd must be asserted low to clear the latch. 7.3.2.4 undervoltage protection (uvp) and power-on reset (por) the uvp and por circuits of the drv841x2 fully protect the device in any power-up/down and brownout situation. while powering up, the por circuit resets the overcurrent circuit and ensures that all circuits are fully operational when the gvdd_x and vdd supply voltages reach 9.8 v (typical). although gvdd_x and vdd are independently monitored, a supply voltage drop below the uvp threshold on any vdd or gvdd_x pin results in all half-bridge outputs immediately being set in the high-impedance (hi-z) state and fault being asserted low. the device automatically resumes operation when all supply voltage on the bootstrap capacitors have increased above the uvp threshold. 7.3.3 device reset two reset pins are provided for independent control of half-bridges a/b and c/d. when reset_ab is asserted low, all four power-stage fets in half-bridges a and b are forced into a high-impedance (hi-z) state. likewise, asserting reset_cd low forces all four power-stage fets in half-bridges c and d into a high- impedance state. to accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs. a rising-edge transition on reset input allows the device to resume operation after a shut-down fault. for example, when either or both half-bridge a and b have oc shutdown, a low to high transition of reset_ab pin will clear the fault and fault pin; when either or both half-bridge c and d have oc shutdown, a low to high transition of reset_cd pin will clear the fault and fault pin as well. when an otsd occurs, both reset_ab and reset_cd need to have a low to high transition to clear the fault and fault signal. 14 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 7.4 device functional modes the drv841x2 supports four different modes of operation: 1. dual full bridges (fb) (two pwm inputs each full bridge) or four half bridges (hb) with cbc current limit 2. dual full bridges (two pwm inputs each full bridge) or four half bridges with oc latching shutdown (no cbc current limit) 3. parallel full bridge (pfb) with cbc current limit 4. dual full bridges (one pwm input each full bridge) with cbc current limit in mode 1 and 2, pwm_a controls half bridge a, pwm_b controls half bridge b, and so forth figure 8 shows an application example for full bridge mode operation. in parallel full bridge mode (mode 3), pwm_a controls both half bridges a and b, and pwm_b controls both half bridges c and d, while pwm_c and pwm_d pins are not used (recommended to connect to ground). bridges a and b are synchronized internally (even during cbc), and so are bridges c and d. out_a and out_b should be connected together and out_c and out_d should be connected together after the output inductor or ferrite bead. if reset_ab or reset_cd are low, all four outputs become high-impedance. figure 15 shows an example of parallel full bridge mode connection. in mode 4, one pwm signal controls one full bridge to relieve some i/o resource from mcu, that is, pwm_a controls half bridges a and b and pwm_c controls half bridges c and d. in this mode, the operation of half bridge b is complementary to half bridge a, and the operation of half bridge d is complementary to half bridge c. for example, when pwm_a is high, high side fet in half bridge a and low side fet in half bridge b will be on and low side fet in half bridge a and high side fet in half bridge b will be off. since pwm_b and pwm_d pins are not used in this mode, it is recommended to connect them to ground. in operation modes 1, 2, and 4 (cbc current limit is used), once the cbc current limit is hit, the driver will be deactivated until the next pwm cycle starts. however, in order for the output to be recovered, the pwm input corresponding to that driver in cbc must be toggled. because of this, cbc mode does not support operation when one half-bridge pwm input is tied to dc logic level. because each half bridge has independent supply and ground pins, a shunt sensing resistor can be inserted between pvdd to pvdd_x or gnd_x to gnd (ground plane). a high side shunt resistor between pvdd and pvdd_x is recommended for differential current sensing because a high bias voltage on the low side sensing could affect device operation. if low side sensing has to be used, a shunt resistor value of 10 m or less or sense voltage 100 mv or less is recommended. dashed line: normal operation; solid line: cbc event figure 6. cycle-by-cycle operation with high-side oc copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: drv8412 drv8432 pwm_hs pwm_ls load current current limit t_hs t_oc pvdd gnd_x pwm_hs pwm_ls load t_ls cbc with high side oc during t_oc period
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com dashed line: normal operation; solid line: cbc event figure 7. cycle-by-cycle operation with low-side oc 16 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432 pwm_hs pwm_ls load current current limit cbc with low side oc t_ls t_oc pvdd gnd_x during t_oc period pwm_hs pwm_ls load t_hs
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the drv841x2 devices are typically used to drive 2 brushed dc or 1 stepper motor. the drv841x2 can be used for stepper motor applications as illustrated in figure 16 ; they can be also used in three phase permanent magnet synchronous motor (pmsm) and sinewave brushless dc motor applications. figure 17 shows an example of a tec driver application. the same configuration can also be used for dc output applications. 8.2 typical applications 8.2.1 full bridge mode operation figure 8. application diagram example for full bridge mode operation schematic copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: drv8412 drv8432 gvdd gvdd pvdd pvdd 1000 uf 3.3 10 nf 100 nf 100 nf100 nf 100 nf 1uf 1uf 1uf 1uf 1uf 100 nf 47 uf 330 uf m m controller (msp430 c2000 or stellaris mcu) reset_ab pwm_b oc_adj gnd gnd_a gnd_b out_b pvdd_b agnd vreg m3m2 bst_b bst_c pvdd_c out_c reset_cd pwm_d vdd gvdd_c out_d pvdd_d bst_d gvdd_d pwm_c gnd_d m1 gnd_c gvdd_b otw fault pwm_a gvdd_a bst_a pvdd_a out_a rsense_ab (option) rsense_cd (option) 100nf 100nf 100nf 100nf roc_adj 1
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 8.2.1.1 design requirements this section describes design considerations. table 3. design parameters design parameter reference example value motor voltage pvdd_x 24 v motor current (peak and rms) i pvdd 6-a peak, 3a rms overcurrent threshold oc th oc_adj = 27 k ? , 9.7 a bridge mode m1m2 parallel full bridge 8.2.1.2 detailed design procedure 8.2.1.2.1 motor voltage higher voltages generally have the advantage of causing current to change faster through the inductive windings, which allows for higher rpms. lower voltages allow for more accurate control of phase currents. 8.2.1.2.2 current requirement of 12-v power supply the drv83x2 requires a 12-v power supply for gvdd and vdd pins. the total supply current is relatively low at room temperature (less than 50 ma), but the current could increase significantly when the device temperature goes too high (for example, above 125 c), especially at heavy load conditions due to substrate current collection by 12-v guard rings. ti recommends designing the 12-v power supply with a current capability at least 5-10% of the load current, and no less than 100 ma to assure the device performance across all temperature ranges. 8.2.1.2.3 voltage of decoupling capacitor the voltage of the decoupling capacitors should be selected in accordance with good design practices. temperature, ripple current, and voltage overshoot must be considered. the high frequency decoupling capacitor should use ceramic capacitor with x5r or better rating. for a 50-v application, a minimum voltage rating of 63 v is recommended. 8.2.1.2.4 overcurrent threshold when choosing the resistor value for oc_adj, consider the peak current allowed under normal system behavior, the resistor tolerance, and that the table 2 currents have a 10% tolerance. for example, if 6 a is the highest system current allowed across all normal behavior, a 27-k ? oc_adj resistor with 10% tolerance is a reasonable choice, as it would set the oc th to approximately 8 a to 12 a. 8.2.1.2.5 sense resistor for optimal performance, the sense resistor must be: ? surface-mount ? low inductance ? rated for high enough power ? placed closely to the motor driver the power dissipated by the sense resistor equals i rms 2 x r. for example, if peak motor current is 3 a, rms motor current is 2 a, and a 0.05- ? sense resistor is used, the resistor will dissipate 2 a 2 0.05 ? = 0.2 w. the power increases quickly with higher current levels. resistors typically have a rated power within some ambient temperature range, along with a de-rated power curve for high ambient temperatures. when a pcb is shared with other components generating heat, margin should be added. always measure the actual sense resistor temperature in a final system, along with the power mosfets, as those are often the hottest components. because power resistors are larger and more expensive than standard resistors, use multiple standard resistors in parallel, between the sense node and ground. this distributes the current and heat dissipation. 18 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 8.2.1.3 application curves figure 9. brushed dc driving figure 10. stepper control, full stepping, 24 v figure 11. stepper control, full stepping, 12v figure 12. stepper control, half stepping, 12v figure 14. pwm_a to outa figure 13. stepper control, 128 microstepping, 12v copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 8.2.2 parallel full bridge mode operation pwm_a controls out_a and out_b; pwm_b controls out_c and out_d. figure 15. application diagram example for parallel full bridge mode operation schematic 20 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432 gvdd gvdd pvdd pvdd 1000 uf loc loc loc loc 3.3 10 nf 100 nf 100 nf100 nf 100 nf 1uf 1uf 1uf 1uf 1uf 100 nf 47 uf 330 uf m controller (msp430 c2000 or stellaris mcu) reset_ab pwm_b oc_adj gnd gnd_agnd_b out_b pvdd_b agnd vreg m3m2 bst_b bst_c pvdd_c out_c reset_cd pwm_d vdd gvdd_c out_d pvdd_d bst_d gvdd_d pwm_c gnd_d m1 gnd_c gvdd_b otw fault pwm_a gvdd_a bst_a pvdd_a out_a rsense_ab (option) rsense_cd (option) 100nf 100nf 100nf 100nf roc_adj 1
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 8.2.3 stepper motor operation figure 16. application diagram example for stepper motor operation schematic copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: drv8412 drv8432 gvdd gvdd pvdd pvdd 1000 uf 3.3 10 nf 100 nf 100 nf100 nf 100 nf 1uf 1uf 1uf 1uf 1uf 100 nf 47 uf 330 uf controller (msp430 c2000 or stellaris mcu) reset_ab pwm_b oc_adj gnd gnd_agnd_b out_b pvdd_b agnd vreg m3m2 bst_b bst_c pvdd_c out_c reset_cd pwm_d vdd gvdd_c out_d pvdd_d bst_d gvdd_d pwm_c gnd_d m1 gnd_c gvdd_b otw fault pwm_a gvdd_a bst_a pvdd_a out_a 100nf 100nf 100nf 100nf m roc_adj 1
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 8.2.4 tec driver figure 17. application diagram example for tec driver schematic 22 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432 gvdd gvdd pvdd pvdd 1000 uf 4.7 uh 4.7 uh 4.7 uh 4.7 uh 3.3 10 nf 100 nf 100 nf 100 nf 100 nf 1uf 1uf 1uf 1uf 1uf 100 nf 47 uf 330 uf tec controller reset_ab pwm_b oc_adj gnd gnd_agnd_b out_b pvdd_b agnd vreg m3m2 bst_b bst_c pvdd_c out_c reset_cd pwm_d vdd gvdd_c out_d pvdd_d bst_d gvdd_d pwm_c gnd_d m1 gnd_c gvdd_b otw fault pwm_a gvdd_a bst_a pvdd_a out_a 100nf 100nf 100nf 100nf 47 uf 47 uf 47 uf 47 uf tec 47 uf 1 roc_adj
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 8.2.5 led lighting driver figure 18. application diagram example for led lighting driver schematic copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: drv8412 drv8432 reset_ab drv8412 reset_cdpwm_a pwm_b pwm_c pwm_d fault otw oc_adjm1 m2 m3 agndgnd gnd_a gnd_b gnd_c gnd_d gvdd_a gvdd_b gvdd_c gvdd_d vdd pvdd_a pvdd_b pvdd_c pvdd_d bst_a out_a bst_b bst_c bst_d out_b out_c out_d vreg 12v up to 50v v in v led
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 9 power supply recommendations 9.1 bulk capacitance having an appropriate local bulk capacitance is an important factor in motor drive system design. it is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. the amount of local capacitance needed depends on a variety of factors, including: ? the highest current required by the motor system ? the power supply ? s capacitance and ability to source current ? the amount of parasitic inductance between the power supply and motor system ? the acceptable voltage ripple ? the type of motor used (brushed dc, brushless dc, stepper) ? the motor braking method the inductance between the power supply and the motor drive system limits the rate current can change from the power supply. if the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. when adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. the data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. figure 19. example setup of motor drive system with external power supply the voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. 9.2 power supplies to facilitate system design, the drv841x2 needs only a 12-v supply in addition to h-bridge power supply (pvdd). an internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. additionally, the high-side gate drive requires a floating voltage supply, which is accommodated by built- in bootstrap circuitry requiring external bootstrap capacitor. to provide symmetrical electrical characteristics, the pwm signal path, including gate drive and output stage, is designed as identical, independent half-bridges. for this reason, each half-bridge has a separate gate drive supply (gvdd_x), a bootstrap pin (bst_x), and a power-stage supply pin (pvdd_x). furthermore, an additional pin (vdd) is provided as supply for all common circuits. special attention should be paid to place all decoupling capacitors as close to their associated pins as possible. in general, inductance between the power supply pins and decoupling capacitors must be avoided. furthermore, decoupling capacitors need a short ground path back to the device. 24 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432 local bulk capacitor parasitic wire inductance + motor driver power supply motor drive system vm gnd + ic bypass capacitor
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 power supplies (continued) for a properly functioning bootstrap circuit, a small ceramic capacitor (an x5r or better) must be connected from each bootstrap pin (bst_x) to the power-stage output pin (out_x). when the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (gvdd_x) and the bootstrap pin. when the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. in an application with pwm switching frequencies in the range from 10 khz to 500 khz, the use of 100-nf ceramic capacitors (x5r or better), size 0603 or 0805, is recommended for the bootstrap supply. these 100-nf capacitors ensure sufficient energy storage, even during minimal pwm duty cycles, to keep the high-side power stage fet fully turned on during the remaining part of the pwm cycle. in an application running at a switching frequency lower than 10 khz, the bootstrap capacitor might need to be increased in value. special attention should be paid to the power-stage power supply; this includes component selection, pcb placement, and routing. as indicated, each half-bridge has independent power-stage supply pin (pvdd_x). for optimal electrical performance, emi compliance, and system reliability, it is important that each pvdd_x pin is decoupled with a ceramic capacitor (x5r or better) placed as close as possible to each supply pin. it is recommended to follow the pcb layout of the drv841x2 evm board. the 12-v supply should be from a low-noise, low-output-impedance voltage regulator. likewise, the 50-v power- stage supply is assumed to have low output impedance and low noise. the power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. moreover, the drv841x2 is fully protected against erroneous power-stage turn-on due to parasitic gate charging. thus, voltage-supply ramp rates (dv/dt) are non-critical within the specified voltage range (see recommended operating conditions of this data sheet). 9.3 system power-up and power-down sequence 9.3.1 powering up the drv841x2 does not require a power-up sequence. the outputs of the h-bridges remain in a high impedance state until the gate-drive supply voltage gvdd_x and vdd voltage are above the undervoltage protection (uvp) voltage threshold (see the electrical characteristics section of this data sheet). although not specifically required, holding reset_ab and reset_cd in a low state while powering up the device is recommended. this allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. 9.3.2 powering down the drv841x2 does not require a power-down sequence. the device remains fully operational as long as the gate-drive supply (gvdd_x) voltage and vdd voltage are above the uvp voltage threshold (see the electrical characteristics section of this data sheet). although not specifically required, it is a good practice to hold reset_ab and reset_cd low during power down to prevent any unknown state during this transition. 9.4 system design recommendations 9.4.1 vreg pin the vreg pin is used for internal logic and not recommended to be used as a voltage source for external circuitry. 9.4.2 vdd pin the transient current in vdd pin could be significantly higher than average current through that pin. a low resistive path to gvdd should be used. a 22- f to 47- f capacitor should be placed on vdd pin beside the 100-nf to 1- f decoupling capacitor to provide a constant voltage during transient. 9.4.3 otw pin otw reporting indicates the device approaching high junction temperature. this signal can be used with mcu to decrease system power when otw is low in order to prevent ot shut down at a higher temperature. copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 25 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com system design recommendations (continued) 9.4.4 mode select pin mode select pins (m1, m2, and m3) should be connected to either vreg (for logic high) or agnd for logic low. it is not recommended to connect mode pins to board ground if 1- resistor is used between agnd and gnd. 9.4.5 parallel mode operation for a device operated in parallel mode, a minimum of 30 nh to 100 nh inductance or a ferrite bead is required after the output pins (for example, out_a and out_b) before connecting the two channels together. this will help to prevent any shoot through between two paralleled channels during switching transient due to mismatch of paralleled channels (for example, processor variation, unsymmetrical pcb layout, etc). 9.4.6 tec driver application for tec driver or other non-motor related applications (for example, resistive load or dc output), a low-pass lc filter can be used to meet the requirement. 26 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 10 layout 10.1 layout guidelines 10.1.1 pcb material recommendation fr-4 glass epoxy material with 2 oz. copper on both top and bottom layer is recommended for improved thermal performance (better heat sinking) and less noise susceptibility (lower pcb trace inductance). 10.1.2 ground plane because of the power level of these devices, it is recommended to use a big unbroken single ground plane for the whole system / board. the ground plane can be easily made at bottom pcb layer. in order to minimize the impedance and inductance of ground traces, the traces from ground pins should keep as short and wide as possible before connected to bottom ground plane through vias. multiple vias are suggested to reduce the impedance of vias. try to clear the space around the device as much as possible especially at bottom pcb side to improve the heat spreading. 10.1.3 decoupling capacitor high frequency decoupling capacitors (100 nf) on pvdd_x pins should be placed close to these pins and with a short ground return path to minimize the inductance on the pcb trace. 10.1.4 agnd agnd is a localized internal ground for logic signals. a 1- resistor is recommended to be connected between gnd and agnd to isolate the noise from board ground to agnd. there are other two components are connected to this local ground: 0.1- f capacitor between vreg to agnd and roc_adj resistor between oc_adj and agnd. capacitor for vreg should be placed close to vreg and agnd pin and connected without vias. 10.2 layout example 10.2.1 current shunt resistor if current shunt resistor is connected between gnd_x to gnd or pvdd_x to pvdd, make sure there is only one single path to connect each gnd_x or pvdd_x pin to shunt resistor, and the path is short and symmetrical on each sense path to minimize the measurement error due to additional resistance on the trace. an example of the schematic and pcb layout of drv8412 are shown in figure 20 , figure 21 , and figure 22 . copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 27 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com layout example (continued) figure 20. drv8412 schematic example 28 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432 gnd gnd gnd gnd gnd outd orange outc orange outb orange outa orange gnd gnd gvdd gnd gvdd gnd gnd gnd gnd gnd c16 0805 0.1ufd/100v c19 0805 0.1ufd/100v c21 0805 0.1ufd/100v c24 0805 0.1ufd/100v pvdd pvdd pvdd pvdd r5 0603 47k c10 0603 0.1ufd/16v c9 0603 1.0ufd/16v c14 0603 1.0ufd/16v c13 0603 1.0ufd/16v c11 fc 47ufd/16v + c15 0805 0.1ufd/100v c18 0805 0.1ufd/100v c20 0805 0.1ufd/100v c23 0805 0.1ufd/100v r7 0805 1.0 1/4w c12 0603 0.1ufd/16v u1 powerpad htssop44-ddw 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 drv8412ddw u1 j1 8 7 6 5 4 3 2 1 gnd pvdd 1000ufd/63v c1 vz + red pvdd gnd black 2 1 j2 gray 6a/250v gvdd gnd c5 0603 0.1ufd/16v c4 m 330ufd/16v + gnd 1.0ufd/16v 0603 c8 gvdd gvdd = 12v
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 layout example (continued) t1: pvdd decoupling capacitors c16, c19, c21, and c24 should be placed very close to pvdd_x pins and ground return path. t2: vreg decoupling capacitor c10 should be placed very close to vreg abd agnd pins. t3: clear the space above and below the device as much as possible to improve the thermal spreading. t4: add many vias to reduce the impedance of ground path through top to bottom side. make traces as wide as possible for ground path such as gnd_x path. figure 21. printed circuit board ? top layer copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 29 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com layout example (continued) b1: do not block the heat transfer path at bottom side. clear as much space as possible for better heat spreading. figure 22. printed circuit board ? bottom layer 10.3 thermal considerations the thermally enhanced package provided with the drv8432 is designed to interface directly to heat sink using a thermal interface compound, (for example, ceramique from arctic silver, timtronics 413, and so forth). the heat sink then absorbs heat from the ics and couples it to the local air. it is also a good practice to connect the heatsink to system ground on the pcb board to reduce the ground noise. r ja is a system thermal resistance from junction to ambient air. as such, it is a system parameter with the following components: ? r jc (the thermal resistance from junction to case, or in this example the power pad or heat slug) ? thermal grease thermal resistance ? heat sink thermal resistance 30 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
drv8412 , drv8432 www.ti.com sles242g ? december 2009 ? revised december 2014 thermal considerations (continued) the thermal grease thermal resistance can be calculated from the exposed power pad or heat slug area and the thermal grease manufacturer's area thermal resistance (expressed in c-in 2 /w or c-mm 2 /w). the approximate exposed heat slug size is as follows: ? drv8432, 36-pin psop3 ? ? 0.124 in 2 (80 mm 2 ) the thermal resistance of thermal pads is considered higher than a thin thermal grease layer and is not recommended. thermal tape has an even higher thermal resistance and should not be used at all. heat sink thermal resistance is predicted by the heat sink vendor, modeled using a continuous flow dynamics (cfd) model, or measured. thus the system r ja = r jc + thermal grease resistance + heat sink resistance. see the ti application report, ic package thermal metrics ( spra953 ), for more thermal information. 10.3.1 drv8412 thermal via design recommendation thermal pad of the drv8412 is attached at bottom of device to improve the thermal capability of the device. the thermal pad has to be soldered with a very good coverage on pcb in order to deliver the power specified in the datasheet. the figure below shows the recommended thermal via and land pattern design for the drv8412. for additional information, see ti application report, powerpad made easy ( slma004 ) and powerpad layout guidelines ( sola120 ). figure 23. drv8412 thermal via footprint copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 31 product folder links: drv8412 drv8432
drv8412 , drv8432 sles242g ? december 2009 ? revised december 2014 www.ti.com 11 device and documentation support 11.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 4. related links technical tools & support & parts product folder sample & buy documents software community drv8412 click here click here click here click here click here drv8432 click here click here click here click here click here 11.2 trademarks all trademarks are the property of their respective owners. 11.3 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.4 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 32 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: drv8412 drv8432
package option addendum www.ti.com 7-jul-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples drv8412ddw active htssop ddw 44 35 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 drv8412 drv8412ddwr active htssop ddw 44 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 drv8412 drv8432dkd active hssop dkd 36 29 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr -40 to 85 drv8432 drv8432dkdr active hssop dkd 36 500 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr -40 to 85 drv8432 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 7-jul-2014 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant drv8412ddwr htssop ddw 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 q1 drv8432dkdr hssop dkd 36 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 q1 package materials information www.ti.com 20-aug-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) drv8412ddwr htssop ddw 44 2000 367.0 367.0 45.0 drv8432dkdr hssop dkd 36 500 367.0 367.0 45.0 package materials information www.ti.com 20-aug-2014 pack materials-page 2

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